发明名称 |
Method and apparatus for a digital clock multiplication circuit |
摘要 |
A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable regions. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency. |
申请公布号 |
AU6463300(A) |
申请公布日期 |
2002.02.18 |
申请号 |
AU20000064633 |
申请日期 |
2000.08.04 |
申请人 |
THE NATIONAL UNIVERSITY OF SINGAPORE |
发明人 |
KIN MUN LYE;JURIANTO JOE |
分类号 |
G06F1/10;G06F7/68;H03K5/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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