| 摘要 |
PROBLEM TO BE SOLVED: To obtain such a semiconductor that countermeasure for a software error is taken for a SRAM memory cell. SOLUTION: A SRAM memory cell is constituted by complementary connection of an inverter INV1 constituted of a NMOS transistor NM1 and a PMOS transistor PM1 and an inverter INV2 constituted of a NMOS transistor NM2 and a PMOS transistor PM2, A gate of the NMOS transistor N2 and a gate of the NMOS transistor N2 are connected to storage nodes NA and NB respectively. Thereby, a capacity value of their gate capacity is added to the storage nodes NA and NB. |
