发明名称 MULTILAYER WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To reduce a power source/ground noise caused by fluctuation in electric potential due to simultaneous switching of semiconductor elements, related to a multilayer wiring board comprising orthogonal parallel wirings. SOLUTION: On a first insulating layer I4 comprising a first parallel wirings L1, a second insulating layer I2 comprising a second parallel wirings L2 orthogonal to the first parallel wirings L1 is laminated, while the first and second parallel wirings L1 and L2 are electrically connected together with a through conductors T2 to provide a laminated wiring body. The first and second parallel wirings L1 and L2 comprise signal wirings S1 and S2, power source wirings P1 and P2, and ground wirings G1 and G2, respectively, with a conductivity of the power source wirings P1 and P2 and/or the ground wirings G1 and G2 smaller than that of the signal wirings S1 and S2. The fluctuation in electric potential of the power source wirings P1 and P2 and/or the ground wirings G1 and G2 caused by simultaneous switching of the semiconductor element is attenuated for reduced power source/ground noise.</p>
申请公布号 JP2002050877(A) 申请公布日期 2002.02.15
申请号 JP20000233111 申请日期 2000.08.01
申请人 KYOCERA CORP 发明人 NABE YOSHIHIRO
分类号 H05K3/46;H01L23/12;(IPC1-7):H05K3/46 主分类号 H05K3/46
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