| 摘要 |
<p>PROBLEM TO BE SOLVED: To make each CPU(central processing unit) surely receive interrupt generated from a low order unit in response to the command that the CPU itself issues to the low order unit. SOLUTION: The low order unit 3 is provided with a control part 32 which generates an interrupt signal 441 in the DPRAM 31 for storing bus acquisition signals BG 431, 432 (in this case, BG 431 is active, and BG 432 is inactive) and the CPU unit 2-1 corresponding to the bus acquisition signals stored in the DPRAM 31 in response to the accepted command when having accepted the command from the CPU unit 2-1 (storing data on a data bus 42 in a DPRAM 31).</p> |
