发明名称 MEMORY EVALUATING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a memory evaluating system which can obtain FBM required for defect analyzing and write-in data in a memory mat at the time of fail. SOLUTION: This system is a memory evaluating system in which selection is performed by a test being equivalent to a test of a memory module loaded in a PC, which can analyze a defective device, the system is constituted of a mother board 1 in which a reference device or the like is loaded, an evaluating board 2 in which ASIC or the like is loaded, a memory tester 3, or the like, test devices to be tested DUT1-DUT3 are inserted into sockets 7-9 for the device to be tested, devices DUTA, DUTB for obtaining FBM (for holding write-in data at the time of fail) being a normal product and the same product as a device to be tested are inserted into sockets 10, 11 for obtaining FBM (for holding write-in data at the time of fail), two pieces out of three pieces are selected, the FBM is simultaneously obtained for the DUTA, DUTB, also, write-in data at the time of fail of one piece out of three pieces is held in either of the DUTA, DUTB.
申请公布号 JP2002050195(A) 申请公布日期 2002.02.15
申请号 JP20000235126 申请日期 2000.08.03
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 MIYATA SEISHI;AOKI HIDEYUKI
分类号 G01R31/28;G06F12/16;G11C29/00;G11C29/44;(IPC1-7):G11C29/00 主分类号 G01R31/28
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