摘要 |
The interface has an internal clock (VCO) and a circuit (L1,L2,CT1,XOR) which produces a difference signal (INVERR) between the period of the incoming command signal (Tpwm) and the internal clock. A driving circuit (CTDC,CNA1) adjusts the internal clock to make the difference zero and a pulse width/voltage converting circuit (L4,L5,CT2,CNA2) produces a corrected reference voltage for the alternator regulator. Independent claims are made for the detailed design of the interface circuits
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