DEVICE AND METHOD FOR MANAGING PROCESSOR LOCAL BUS AND COMPUTER PROGRAM PRODUCT

摘要

PROBLEM TO BE SOLVED: To provide improved architecture for an on-chip bus which flexibly and robustly supports various built-in system requirements. SOLUTION: This is a dual-master device which manages a processor local bus(PLB) supporting up to 16 masters as a high-performance on-chip bus used by many system-on-chip(SOC) applications. This device includes a 1st circuit which generates an address phase for read data connected to the PLB and a 2nd circuit which generates an array phase for write data connected to the PLB. The 2nd address phase generating circuit is so constituted as to perform writing operation when a write data bus is idle and a read data bus is busy and vice versa.