| 摘要 |
<p>PROBLEM TO BE SOLVED: To keep processing speed between input of packet data from the outside and output in HDLC frame to line. SOLUTION: Packet data 13 are input by an input interface block 1, FCS is added to it by a FCS attachment block 2, '0' is inserted to it by an insertion block 3, a start flag and an end flag are added by a flag attachment block 4 to turn it into a HDLC frame 14, and the HDLC frame 14 is output by an output interface block 5. A priority processing circuit 6 is made to proceed with the operation of each block, the input interface block 1, the FCS attachment block 2, the insertion block 3, the flag attachment block 4, and the output interface block 5, by raising the priority level to a block which is at farther back stage.</p> |
