| 摘要 |
PROBLEM TO BE SOLVED: To economically realize a processor system capable of executing plural kinds of processor software programs having respectively different architecture elements while maintaining the high performance speed of a single hardware unit. SOLUTION: The processor architecture converter 100 arranged between a memory storing a non-native instruction program and a general execution processor sorts a non-native instruction a acquired from the memory by using information generated by a virtual PC as an address by using an instruction sorting means, reads out instruction synthesis information from an instruction synthesis information memory by using address information previously determined in each sorted group as a reference address and synthesizes a native instruction. Although the selection/switching of a non-native instruction set is executed by selectively switching the activation parts of the instruction sorting means and the instruction synthesis information memory, the activation parts are switched at suitable timing by synchronizing the timing with a switching permission signal outputted from the instruction synthesis information memory.
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