| 摘要 |
The memory device is controlled by a processor and comprises a pin for clock signal input, a set of pins for instructions inputs including a pin for clock validation signal, a pin for the first signal for chip selection as row address pulse, a pin for the second signal for chip selection as column address pulse, a pin for row instruction signal, a pin for column instruction signal, a set of pins for rows addresses inputs, a set of pins for columns addresses inputs, and a set of pins for data input/output. The rows and columns instructions, as well as the rows and columns addresses, are received in response to two consecutive edges of clock signal in synchronism with the first and second signals for chip selection. The first datum of the first signal for chip selection received in response to the first edge of clock signal is recognized as the chip selection signal, and the second datum of the first signal received in response to the second edge of clock signal is recognized as the row address instruction. The first datum of the second signal received in response to the first edge of clock signal is recognized as the chip selection signal, and the second datum of the second signal received in response to the second edge of clock signal is recognized as the column address instruction. The memory system comprises memory modules where semiconductor memory devices (M) are mounted, and a processor controlling the memory devices. The first and second signals for chip selection are generated by the processor and transmitted to each module by different bus lines. The rows and columns instructions are received by the processor by separate bus lines. The rows and columns addresses are received separately from separate address lines. The first and second signals for chip selection are received in passing by separate bus lines.
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