Multi-Bit-Speicherzelle und Verfahren zur Herstellung

摘要

A memory layer (3) for trapping charge carriers which is provided over the source area (6a) and the drain area (6b) is interrupted over the channel, hereby preventing the diffusion of charge carriers that are trapped over the source area and the drain area. The memory layer is limited to areas over the parts of the source area and the drain area that face towards the channel and is completely embedded in oxide.