发明名称 |
Data transfer apparatus and microcomputer |
摘要 |
A selective output circuit of a DMA controller selectively outputs either an address change amount relevant to the transfer data size or an address change amount independent of the transfer data size to a second input port of an adder with reference to settings of control register. The adder has a first input port for receiving an address value being set in a source address register and a second input port for receiving the selected address change amount, and is arranged so as to output a summed-up result to the source address register.
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申请公布号 |
US2002019917(A1) |
申请公布日期 |
2002.02.14 |
申请号 |
US20010897415 |
申请日期 |
2001.07.03 |
申请人 |
TESHIMA YOSHINORI;FUJII HIROSHI;ISHIHARA HIDEAKI |
发明人 |
TESHIMA YOSHINORI;FUJII HIROSHI;ISHIHARA HIDEAKI |
分类号 |
G06F13/12;G06F12/02;G06F13/28;(IPC1-7):G06F13/28 |
主分类号 |
G06F13/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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