发明名称 |
DRAM memory cell for DRAM memory device and method for manufacturing it |
摘要 |
DRAM memory cell for a DRAM memory having: a MOSFET selection transistor which has a drain region and a source region in a semiconductor substrate column (3), a current channel which runs in the vertical direction between the drain and source regions and which can be actuated by a control gate electrode (10) being provided; a capacitor which is stacked under the MOSFET selection transistor and is electrically connected to the source region in the semiconductor substrate column (3); a metal bit line (20) which is located above the MOSFET selection transistor and is electrically connected to the drain region in the semiconductor substrate column (3), a metal word line (9) which makes electrical contact directly with the control gate electrode (10) of the MOSFET selection transistor [lacuna], the metal word line (9) extending perpendicularly with respect to the metal bit line (20) which makes electrical contact in a direct and self-aligning fashion with the drain region of the semiconductor substrate column (3).
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申请公布号 |
US2002017668(A1) |
申请公布日期 |
2002.02.14 |
申请号 |
US20010875803 |
申请日期 |
2001.06.06 |
申请人 |
HOFMANN FRANZ;SCHLOSSER TILL |
发明人 |
HOFMANN FRANZ;SCHLOSSER TILL |
分类号 |
H01L21/8242;H01L27/108;H01L27/12;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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