| 摘要 |
The invention relates to a circuit with low parasitic inductances, reduced current flow paths, and reduced current-circumfusion. The circuit includes a ceramic substrate supporting mutually insulated metallic connection webs and a first and a second series-connected power switch. Each power switch includes a first and a second power transistor connected in parallel and DC and AC leads. The insulation layer separates the conduction webs from a supporting substrate and is effective to minimize any parasitic inductances in the circuit arrangement.
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