GATE TECHNOLOGY FOR STRAINED SURFACE CHANNEL AND STRAINED BURIED CHANNEL MOSFET DEVICES

摘要

A semiconductor structure including a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, and a sacrificial Si1-yGey layer. The sacrificial Si1-yGey layer is removed before providing a dielectric layer. The dielectric layer includes a gate dielectric of a MOSFET. In alternative embodiements, the structure includes a Si1-zGey spacer layer and a Si layer. In another embodiment of the invention there is provided a method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer.