| 摘要 |
The PLL circuit (1) includes means (2) for producing a first to an n-th (n being an integer equal to or greater than 2) reference signals (FR1 to FR13), a first variable frequency-dividing means (8) for dividing, at a timing according to the phase of the first reference signal (FR1), the frequency of an output (VO) of a voltage-controlled oscillator (6) generating a signal having a frequency responsive to a supplied control voltage (CV) to produce a first feedback signal (FP1), a second variable frequency dividing means (9) for frequency dividing, at timings according to the phases of the second to the n-th reference signals (FR2 to FR13) the output (VO) of the voltage-controlled oscillator (6) to produce a second to an n-th feedback signals (FP2 to FP13), a phase comparing means (A1 to A13) for comparing the phases of the first to the n-th reference signals (FR1 to FR13) with the phases of the first to the n-th feedback signals (FP1 to FP13) to produce a first to an n-th error signals (ER1 to ER13) and a control signal producing means (21) for producing the control signal (CV) from the first to the n-th error signals (ER1 to ER13) output from the phase comparing means. The PLL circuit (1) functions to synchronize the first reference signal with the first feedback signal in phase after a phase difference between at least one of the first to the n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. A frequency-division ratio of the second variable frequency dividing means (9) is 1/n the frequency-division ratio of the first variable frequency dividing means (8).
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