发明名称 Pll circuit
摘要 <p>BPF having a band width of reference signal fREF - mixer output signal fMIX OUT is connected to a phase comparator. When an output signal corresponding to the passage of this band width has been obtained, a changeover switch is turned OFF. Upon detection such that the PLL circuit is unlockable, an output signal is obtained from an offset differential pair circuit, the changeover switch is turned ON, and the time constant of LPF is reduced to shorten the lock-up time, and the voltage applied to VCO is made larger than the usual voltage. By virtue of this construction, a PLL circuit of an analog system can be realized which can shorten the lock-up time and, in addition, can reduce noise and harmonic spurious. <IMAGE></p>
申请公布号 EP1179888(A1) 申请公布日期 2002.02.13
申请号 EP20010118698 申请日期 2001.08.03
申请人 NEC CORPORATION 发明人 MATSUI, NAOHIRO
分类号 H03L7/16;H03L7/093;H03L7/095;H03L7/10;H03L7/107;(IPC1-7):H03L7/113 主分类号 H03L7/16
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