| 摘要 |
A data input/output circuit preferably used in a fast interface system such as Rambus(TM) interface or SyncLink(TM) interface for transmitting and/or receiving data in synchronization with a supplied clock. The data input/output circuit has a phase locked loop (PLL) circuit for differentially receiving the clock and a reference voltage to generate an internal clock having a predetermined phase delay with respect to the supplied clock, a register for storing setting data for changeably setting the level of the reference voltage, and a level shift circuit for setting the level of the reference voltage to be supplied to the PLL circuit to a predetermined value in accordance with the setting data stored in the register, and performs actual data transmission/reception processing in synchronization with the internal clock. The data input/output circuit optimally sets the level of the reference voltage to be supplied to the PLL circuit at the initial setting prior to data transmission/reception to optimize a margin in the internal clock.
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