| 摘要 |
In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10OMEGA to 320OMEGA, thereby reducing a quartz current and obtaining a required negative resistance.
|
