发明名称 System for optimizing the testing and repair time of a defective integrated circuit
摘要 A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
申请公布号 US6347386(B1) 申请公布日期 2002.02.12
申请号 US20000612098 申请日期 2000.07.07
申请人 MICRON TECHNOLOGY, INC. 发明人 BEFFA RAY
分类号 G01R31/28;G01R31/3183;G01R31/319;G06F11/00;G11C29/00;G11C29/08;G11C29/10;G11C29/26;G11C29/44;G11C29/56;H01L21/66;(IPC1-7):G11C29/00 主分类号 G01R31/28
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