发明名称 VARIABLE FREQUENCY DIVIDER CIRCUIT, AND CLOCK FREQUENCY DIVISION METHOD USING THE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a variable frequency divider circuit that is synchronized with an input reference clock and provides frequency division clocks with a different frequency division ratio and to provide a clock frequency division method using the circuit. SOLUTION: The variable frequency divider circuit comprises frequency divider circuit sections 12, 14 with a different frequency division ratio that receive input reference clocks, a selection section 16 that selects and outputs a frequency division clock from the frequency divider circuit sections 12, 14, and a control section 22 that monitors the frequency division clock of the frequency divider circuit sections 12, 14 to control the selection of the selection section 16 on the basis of it.
申请公布号 JP2002043929(A) 申请公布日期 2002.02.08
申请号 JP20000228055 申请日期 2000.07.28
申请人 NEC ENG LTD 发明人 MAKISHITA YUUJI
分类号 G06F1/08;H03K21/00;H03K23/64;H03L7/085 主分类号 G06F1/08
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