发明名称 CHATTERING ELIMINATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a chattering elimination circuit that surely eliminates a chattering noise without causing malfunctions in chattering elimination due to the timing of chattering. SOLUTION: When a switch 6 is open, an output of an exclusive OR circuit 3 goes to a logical high level that triggers a monostable multivibrator 2, which gives a clock signal to a D flip-flop circuit 1 to allow the flip-flop circuit 1 to provide an output of a logical high level. When the switch 6 is closed and chattering takes place at the closing, the supply of the clock signal to the D flip-flop circuit 1 is stopped, the output of the D flip-flop circuit 1 goes to a logical low level at the point after a lapse of a prescribed time T from the point when the chattering is lost and a signal from which the chattering noise is eliminated is obtained.
申请公布号 JP2002043902(A) 申请公布日期 2002.02.08
申请号 JP20000218904 申请日期 2000.07.19
申请人 NEW JAPAN RADIO CO LTD 发明人 NOMURA REONA
分类号 H03K5/1254 主分类号 H03K5/1254
代理机构 代理人
主权项
地址