CLOCK GENERATING CIRCUIT, ITS CONTROL METHOD, AND SEMICONDUCTOR STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To realize a clock generating circuit, which avoids deviation in duty of output clocks that becomes the problem in phase control and conducts a more precise phase control, by only adding a simple circuit. SOLUTION: A clock duty adjusting circuit (102) is provided in the poststage of a variable delay circuit (101). The circuit (102) controls the amount of delay of the circuit (101) by the rising edge of a clock and adjusts the pulse widths of the signals by the falling edge when the phase of the rising edge coincides with reference clocks. Thus, the duty of output clocks is mateched with the duty of the reference clocks.