发明名称 POWER SUPPLY WIRING DESIGNING METHOD OR SEMICONDUCTOR CHIP, AND COMPUTER-READABLE RECORDING MEDIUM WITH PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE SAME METHOD RECORDED THEREON
摘要 PROBLEM TO BE SOLVED: To arrange a logically determined function block and a logically non-determined function block on a semiconductor chip and to design power supply wiring optimal for these blocks. SOLUTION: On the basis of power consumption information obtained from the operating frequency of the logically non-determined function block, the operation rate, the power supply voltage to be used, the number of gates, the peripheral temperature and current density, a power supply wiring width required inside the logically non-determined function block is obtained and while using that width, the area of the logically non-determined function block is determined. Besides, on a high-order hierarchy, power supply wiring is temporarily laid between the logically determined function block and the logically non-determined function block. On the assumption that a current source is connected to the power supply terminal of the logically non-determined function block, the resistant net of power supply wiring inside the logically non-determined function block is prepared and while using the local resistant net, the resistant net of entire power supply wiring on the high-order hierarchy is prepared. By analyzing the net, the optimal line width of power supply wiring is determined and on the basis of that line width, power supply wiring on the high-order hierarchy is laid again.
申请公布号 JP2002041590(A) 申请公布日期 2002.02.08
申请号 JP20000225600 申请日期 2000.07.26
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 SUZUKI KENJI;SAKANO KOJI;OSAJIMA TOORU;YONEDA TAKASHI;NAWA TAKAMICHI;TSUNETO YASUSHI;INUI MASUO;YAMAMOTO HIROYUKI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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