| 摘要 |
PROBLEM TO BE SOLVED: To speed up operation of a power/remainder arithmetic circuit for encryption and to improve tamper-resistance against it. SOLUTION: Three multiplication/remainder arithmetic circuits 1-3 are arranged for two power/remainder arithmetic operations. The two power/ remainder arithmetic operations are divided into two to four processing of two quadratic residue arithmetic operations and zero to two multiplication/ remainder arithmetic operations for each digit of the exponents. When an exponent is O-bit, the multiplication/remainder arithmetic operation is not carried out. According to the number of bits of each digit of the exponents B1, B2, the two to four processing are sequentially allotted to the three multiplication/ remainder arithmetic circuits. Also in the case of digits of which both of the exponents B1, B2 are 1, a wait state rarely occurs, and the two power/remainder arithmetic operations can speedily be executed. The bit patterns of the exponents cannot be known from the operations of the arithmetic circuits.
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