发明名称 SEMICONDUCTOR TEST APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor test apparatus in which the SCAN operation time can be shortened by improving a SCAN operation in relieving and analyzing operation so that a read-modify-write-operation is performed only when an FAIL exists. SOLUTION: This apparatus is provided with a memory for counting for rows for storing and updating the number of times of occurrence of defective cells for each row address line by a read-modify-write-operation, a memory for counting for columns for storing and updating the number of times of occurrence of defective cells for each column address line by a read-modify-write- operation, and a means for controlling the operation so that, in SCAN operation, when fail information read out from AFM detects that fail does not exist, the read-modify-write-operation of the memory for counting is not performed, but only a read-operation is performed, and then read-out of the address is performed. The operation speed of count processing of the SCAN operation in the relieving and analyzing operation is thus increased.
申请公布号 JP2002042490(A) 申请公布日期 2002.02.08
申请号 JP20000227556 申请日期 2000.07.24
申请人 ADVANTEST CORP 发明人 SATOU SHINYA
分类号 G01R31/28;G11C29/00;G11C29/44;(IPC1-7):G11C29/00 主分类号 G01R31/28
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