发明名称 REMAINDER ARITHMETIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem that a traditional dividing arithmetic circuit becomes large in terms of scale of circuit as a division is performed by repetitive operations and takes too much operation time. SOLUTION: In the remainder arithmetic circuit, a divisor div is divided into an odd number div1 and an even number div0 and the division by the even number and the division by the odd number are performed separately. The division by the even number div0 is realized by dividing a dividend A into the high order bits and the low order bits. The division by the odd number div1 divides the odd number div1 into a quotient A0 obtained by the division by the even number div0. The respective operation in a division by the odd number can be reduced through the use of addition. Mod, a remainder can be obtained by connecting solutions, mod0 and mod1 obtained in the above, Thereby a high speed remainder arithmetic circuit with small scale of circuit can be realized.
申请公布号 JP2002041282(A) 申请公布日期 2002.02.08
申请号 JP20000227154 申请日期 2000.07.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YASUNAGA KOTA
分类号 G06F7/72;(IPC1-7):G06F7/72 主分类号 G06F7/72
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