SEMICONDUCTOR MEMORY DEVICE WITH SENSE AMP CONTROL CIRCUIT FOR DETECTING BIT LINE FAILURE AND CONTROL METHOD THEREFOR

摘要

PURPOSE: A semiconductor memory device with a sense amp control circuit for detecting bit line failure and a control method therefor are provided to effectively detect a failure in a bit line bridge by differently setting sensing time at bit lines. CONSTITUTION: A RAS(row address strobe signal) delay(300) delays a row address strobe signal(/RAS) by a predetermined time and outputs a delayed RAS signal(D_RAS). A sense amp control signal generator(310) generates first and second sense amp control signals which are generated in response to the delayed RAS signal(D_RAS) and a predetermined test mode control signal and are enabled in same timing or different timings in accordance with the operational modes of the semiconductor memory device. First sense amps(320) sense and amplify the potential of (2N-1)th bit line pairs in response to the first sense amp control signal. Second sense amps(330) sense and amplify the potential of 2N-th bit line pairs in response to the second sense amp control signal.