发明名称 SEMICONDUCTOR WAFER HAVING TEST PATTERN, METHOD FOR INSPECTING SEMICONDUCTOR WAFER, METHOD FOR MANAGING MANUFACTURING PROCESS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR
摘要 PROBLEM TO BE SOLVED: To provide a test pattern with which a circuit pattern can be inspected for defects with high sensitivity in a semiconductor manufacturing process, a method for detecting defect, and a method for managing manufacturing process both of which use the test pattern. SOLUTION: The variation of the misalignment amounts of an interlayer pattern is monitored from the occurring amounts of defects in the misalignment amounts of a plurality of test patterns having different misalignment amounts. Alternatively, defects such as short circuits, continuity defects, short circuits caused by foreign matters, etc., are detected by forming test patterns having different circuit patterns.
申请公布号 JP2002043385(A) 申请公布日期 2002.02.08
申请号 JP20000226859 申请日期 2000.07.27
申请人 HITACHI LTD 发明人 TANAKA MAKI;WATANABE MASAHIRO;HIROI TAKASHI;SHISHIDO CHIE;KUNI TOMOHIRO;WATANABE KENJI;SUGIMOTO ARITOSHI;NOZOE MARI
分类号 G01R31/28;H01L21/66;H01L21/822;H01L27/04;(IPC1-7):H01L21/66 主分类号 G01R31/28
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