发明名称 PROCESS FOR MANUFACTURING INTEGRATED CIRCUIT HAVING DUAL DAMASCENE STRUCTURE AND CAPACITOR
摘要 PROBLEM TO BE SOLVED: To provide a side-wall capacitor in an integrated circuit including a dual damascene structure. SOLUTION: A process for forming the dual damascene structure and the capacitor includes forming of a stack having an insulating layer and a stopping layer (steps 10-25). The stack is pattern-formed (step 30) so as to form an opening part which is used in order to form the side-wall capacitor (step 35) when a via or a groove of the dual damascene structure is formed. As a result, the process for manufacturing the side-wall capacitor can be integrated with the dual damascene process without adding a further mask or etching process.
申请公布号 JP2002043433(A) 申请公布日期 2002.02.08
申请号 JP20010181366 申请日期 2001.06.15
申请人 AGERE SYSTEMS GUARDIAN CORP 发明人 CHITTIPEDDI SAILESH
分类号 H01L21/768;H01L21/02;H01L21/3205;H01L21/822;H01L23/52;H01L27/04;(IPC1-7):H01L21/822;H01L21/320 主分类号 H01L21/768
代理机构 代理人
主权项
地址