TEST APPARATUS FOR SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory test apparatus in which the defect relieving and analyzing time is shortened. SOLUTION: This semiconductor memory test apparatus for analyzing a defective memory cell of a DUT in a defect relieving and analyzing section and replacing as defective memory cell by a spare memory cell is provided with: a fail memory of an address fail memory for transferring the normal/ defective conditions of a plurality of bits existing in the same address as an address having a defective memory cell of the DUT to a fail buffer memory of the defect relieving and analyzing section with the prescribed format; and a fail buffer memory of the defect relieving and analyzing section for storing the prescribed format data.