| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a synchronizing signal generation circuit, in which overhead in synchronizing a processor with a coprocessor is reduced. SOLUTION: This synchronizing signal generation circuit includes an access inhibited region register 50 for designating the access inhibited region of the processor in a shared memory, a comparator circuit 51 for detecting that the processor accesses the access inhibited region designated by the register 50, a NAND circuit 53 for generating a P-DC signal for keeping the processor in waiting state, on the basis of a coprocessor instruction performance signal and the comparison results of the circuit 51 and an AND circuit 54. Then a wasteful processing cycle by the processor is no longer needed, and its overhead can be reduced.</p> |
