REDUNDANCY RELIEVING CIRCUIT AND METHOD, AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a redundancy relieving circuit and a method therefor, and semiconductor device in which the test time for testing a defective memory cell is shortened, the test device is made inexpensive by dispensing with fail memories having extensive capacity accumulating defective bits, and the device can easily cope with the increase and decrease of the number of IO. SOLUTION: Judgement about many IO output MOUT and an expected value is performed en block, judgement information DOUT of the result is outputted to an error information obtaining device 22, table information is read out successively for every block in an analysis processing device 23 and replacement data are obtained, and the replacement data can be outputted to an external tester in serial through an external I/F circuit 24. Judgement about a redundancy memory cell 4a or the like also and a prescribed expected value can be performed as well as the other memory cells 4 or the like. A relief analysis processing in which a defective redundant memory cell is not used can be performed by outputting this judged result as well as judgement information DOUT for the other memory cells 4 or the like.