发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To enhance the capability of supplying a current of an internal power source voltage generating circuit 14a incorporated in a semiconductor memory only during the time when a latch signal F for latching FUSE setting state of a redundant address setting section is active. SOLUTION: An N channel MOS transistor Nmrs is connected to the gate electrode of a P channel MOS transistor P2 supplying a current to an internal power source VINT from an external power source VCC by using an output transistor of a voltage follower constituting an internal power source voltage generating circuit 14a, and the capability of supplying the current of the P channel MOS transistor P2 is enhanced by reducing the gate potential of the transistor to a ground potential responding to the latch signal F for latching FUSE setting state. Therefore, the potential drop of the internal power source voltage VINT for current consumption at the time of FUSE discrimination is reduced so that the current consumption at the time of standby is not exceeded.
申请公布号 JP2002042486(A) 申请公布日期 2002.02.08
申请号 JP20000225304 申请日期 2000.07.26
申请人 NEC MICROSYSTEMS LTD 发明人 YAMASHITA JUNICHI
分类号 G11C11/407;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/407
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