HIERARCHICAL DESIGN AND TEST METHOD AND SYSTEM, PROGRAM PRODUCT EMBODYING THE METHOD AND INTEGRATED CIRCUIT PRODUCED THEREBY

摘要

A method for use in the hierarchical design of integrated circuits, having a t least one module having functional memory elements and combinational logic, comprises replacing the description of functional memory elements of a modul e with a description of a scannable memory element configurable in scan mode a nd capture mode; partitioning the module into an internal partition and a peripheral partition by converting selected scannable memory elements into peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; arranging the scannable memory elements into scan chains in which peripheral and internal scannable memory elements of the module are controlled by an associated modu le test controller when configured in internal test mode; and peripheral scannable memory elements of the module are controlled by a higher level tes t controller when configured in an external test mode.