| 摘要 |
PURPOSE: A method for fabricating a semiconductor device is provided to reduce junction area of source/drain and thereby to reduce junction capacitance. CONSTITUTION: After a gate oxide layer(22a) is formed on a semiconductor substrate(21), a gate pattern is formed with a stack of a polysilicon layer(23a) and a cap oxide layer(24b) on the gate oxide layer(22a). By lightly implanting ion impurities through the first mask layer, an LDD region(26) is formed in the substrate(21). A sidewall spacer(27) is then formed on a side surface of the gate pattern, and the gate oxide layer(22a) is selectively etched through the second mask layer. Next, a polysilicon layer(29) doped with N+ or P+ impurities is formed on a resultant structure and then polished to a height of the middle of the cap oxide layer(24b). The doped polysilicon layer(29) is then selectively removed. A source/drain region(30) with heavy ion impurities is formed by automatic doping from the remaining doped polysilicon layer(29).
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