| 摘要 |
PURPOSE: A tester architecture construction data generating method, a tester architecture construction data generating method and a tester circuit are provided to be suitable for a semiconductor device, which is less reduced in required cost. CONSTITUTION: A tester architecture construction data generating method comprising the steps of: (S11)for extracting and constructing a generation algorithm for a test pattern corresponding to a semiconductor device to be tested is determined, (S12) for analyzing and disassembling the completed test program into the minimum test units, necessary functions being chosen every unit tests to thereby determine the architecture of the most suitable or optimum ALPG, (S13)for describing the ALPG having the determined architecture in a Hardware Description Language(HDL) and (S15)for placing an FPGA and a semiconductor device to be tested on one board by use of data described in HDL.
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