发明名称 Circuit arrangement for the transmission of synchronous information over an asynchronous network, in particular an asynchronous transfer mode network
摘要 <p>In such a device, the information is conveyed by databit packets between a transmitter unit and a receiver unit, each of these packets being formed of an information cell comprising on the one hand a header carrying an address, and on the other hand a useful field carrying the information to be transmitted, the transmitter unit and the receiver unit operating between them in synchronous mode on the basis of respective plesiochronous local clocks. …<??>According to the invention, the device comprises: … …  - means (15) for detecting and compensating for the lengthy fadings in transmission of the flow of information cells received by the receiver unit, …  - means (16) for detecting and compensating for the loss or insertion of cells into the flow of information cells received by the receiver unit, and …  - means (17) for reducing the jitter introduced by the asynchronous transmission of the information in the network and for compensating for the relative plesiochronism of the local clocks of the transmitter unit and of the receiver unit. … …<IMAGE>… </p>
申请公布号 EP0487428(B1) 申请公布日期 2002.02.06
申请号 EP19910403157 申请日期 1991.11.22
申请人 THALES 发明人 SORTON, GERARD;GRENOT, THIERRY
分类号 H04J3/06;H04L7/04;H04L12/70;H04L25/30;H04Q11/04;(IPC1-7):H04L7/00;H04L5/24 主分类号 H04J3/06
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