Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption

摘要

An instruction cache memory (12) includes a clock gate circuit (26) for controlling the supply of a clock signal (CLK) to tag RAM (22). The clock gate circuit (22) supplies the clock signal (CLK) to tag RAM 22 only when there is a movement in cache line for storing a word to be read out or a branch instruction is detected in a processor (14). As a result, power consumption of the tag RAM (22) can be reduced.