| 摘要 |
A microprocessor to control and to prevent failure in mechanisms, particularly those that perform timed intervals of work. The microprocessor controls the length of each interval of work, and limits the mechanism to perform only a predetermined number of work intervals, after which it deactivates the device, allowing the mechanism to reactivate only after entry of a coded number or operation of a key switch. The microprocessor monitors all functions of the mechanism and includes a first failsafe circuit that shuts down the mechanism in the event of malfunction. A second failsafe circuit monitors the first failsafe circuit, and bypasses it to shut down the mechanism in the event of malfunction in the first failsafe circuit.
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