发明名称 |
SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PARASITIC CAPACITANCE CAUSED BY INTERCONNECTION AND MANUFACTURING METHOD THEREOF |
摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to control resistant capacitor delay in an interconnection of a high integrated semiconductor device, by forming an interconnection trench of a uniform depth in a low dielectric organic silicon oxide layer. CONSTITUTION: An inorganic silicon oxide layer(13) and an organic silicon oxide layer(15) are sequentially stacked on a substrate(10). A partial trench(17') having the same depth as the organic silicon oxide layer is formed in the organic silicon oxide layer through a patterning process. An oxygen treatment process is performed regarding the surface of the inner wall of the partial trench. A hydrofluoric acid wet etch is performed regarding the partial trench to complete a trench. |
申请公布号 |
KR20020010310(A) |
申请公布日期 |
2002.02.04 |
申请号 |
KR20000043961 |
申请日期 |
2000.07.29 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
HAN, JAE HYEON;KIM, JAE HAK;SHIN, HONG JAE |
分类号 |
H01L21/28;H01L21/768;H01L23/485;H01L23/522;H01L23/528;H01L23/532;(IPC1-7):H01L21/28 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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