| 摘要 |
PURPOSE: A bit line of a semiconductor device is provided to prevent the increase of parasitic capacitance and the electrical short-circuit between the bit line and a word line, by making a sidewall spacer as an insulation layer function as a passivation layer in an over-etch process. CONSTITUTION: A plurality of active regions, field regions and bit line contact portions are defined in a semiconductor substrate(20). A diffusion region and a plurality of word lines(22) composed of a cap insulation layer(23), a gate line, a gate insulation layer(21) and a gate sidewall spacer are formed in the first direction on the semiconductor substrate. A plurality of plugs and the surface of the cap insulation layer are planarized such that the plurality of plugs completely fill the space between the word lines and are separated form each other. A contact hole is formed to expose a part of the plugs and the cap insulation layer in the bit line contact portion. An interlayer dielectric(260) covering the word line, the rest of the plugs and the surface of the substrate is formed. The passivation layer is formed on the inner side surface of the contact hole to cover the exposed cap insulation layer. A plurality of bit lines(29) are formed in the second direction perpendicular to the first direction, and are in contact with the exposed plug in the bit line contact portion.
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