| 摘要 |
PURPOSE: To provide a semiconductor storage device in which the pull-out of charges from subword lines is conducted at a high speed and the generation of a leak condition of the threshold value voltage Vt of an access MOS transistor in a memory cell is prevented without increasing the chip size. CONSTITUTION: The connection of the source of a MOS transistor 104 and the drain of a MOS transistor 105 is carried out by connection to the signal line of address signals RA00. The connection of the source of a MOS transistor 104' and the drain of a MOS transistor 105' is carried out by connection to address signals RA02. Control signals RANE are inputted into the gate of a MOS transistor 108 and its drain is connected to the signal line of the address signals RA00 and its source is connected to a GND line. Each of the subword lines of the transistors 105 and 105' are connected to a GNDXDEC line and the transistors 105 and 105' are formed by a small gate width holding a ground potential. The MOS transistors 108 and 108' have a gate width from which a current capacity, that rapidly transitions the subword lines from a boosting potential to a ground potential, is obtained.
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