发明名称 |
METHOD OF REDUCING REACTIVE ION ETCHING LAG IN DEEP- TRENCH SILICON ETCHING |
摘要 |
PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained. |
申请公布号 |
JP2002033313(A) |
申请公布日期 |
2002.01.31 |
申请号 |
JP20010161081 |
申请日期 |
2001.05.29 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
NAEEM MUNIR D;MATHAD GANGADHARA S;KIM BYEONG YEOL;KUDELKA STEPHAN P;LEE BRIAN S;LI HONG;MORALES ELIZABETH;PARK YOUNG-JIN;RANADE RAJIV M |
分类号 |
H01L21/302;H01L21/3065;H01L21/308;H01L21/8242;H01L27/108 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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