VOLTAGE LIMITING BIAS CIRCUIT FOR REDUCTION OF HOT ELECTRON DEGRADATION EFFECTS IN MOS CASCODE CIRCUITS

摘要

MOS Cascode amplifier circuit including a voltage limiting bias circuit of additional transistors acting as a series voltage-limiting device between the MOS cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS cascode amplifier circuit output voltage is at its maximum value. The drain-source voltage excursion peak on the sensitive cascode transistor is limited to a value below a pre-selected critical voltage, Vcrt. The additional transistors are connected by internal adjacent source-drain nodes as a sequencial chain with gates biased at respective fixed voltages. The number of additional transistors are selected to limit the peak drain-source voltage excursion on the sensitive transistor under operating conditions.