| 摘要 |
A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a "sea of cells" layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks. The gate array does not contain explicit routing channels; routing is effected using the prewired routing that is integral with each gate array cell.
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