| 摘要 |
In a SRAM, coupling between the adjacent bit lines is reduced and the limitation in reduction of the pattern area per memory cell is relaxed. The SRAM comprises SRAM memory cells arranged in a matrix and forming a cell array, pairs of bit lines BL and /BL extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to the memory cells on the same column of the cell array, and the bit lines of each pair being arranged on both sides of the memory cells on the same column, a grounded line Vss, for supplying a ground potential to the memory cells, formed of the same layer as that of the pairs of bit lines and extending in the column direction, and a power supplying line Vdd, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.
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