| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which erroneous write-in can be suppressed effectively suppressing increment of a write-in time of data for a memory cell. SOLUTION: This semiconductor memory has plural selecting lines and bit lines alternately arranged, plural word lines arranged almost orthogonally intersecting to selecting lines and bit lines, a first electrode connected to the selecting line, a second electrode connected to the bit line, plural MOS transistors having a control electrode connected to the word line and constituting memory cells, a first voltage supply circuit supplying first voltage to the first electrode and connected to the selecting line, and a second voltage supply circuit supplying second voltage varying following variation of the first voltage to the second electrode and connected to the bit line and the selecting line.</p> |
