发明名称 FAULT ANALYZING DEVICE FOR SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To enable to specify existence of troubles, places, the number of them, or the like with a BIST test of only one time without adding complex circuit constitution. SOLUTION: Discrimination of a normal/defective condition is performed successively using a test circuit incorporated in a memory 10 based on address information supplied to the memory 10, consequently, fault discrimination information outputted from a comparing circuit 13 and address information outputted from an address counter circuit 11 are taken successively in a logic scan chain 15 and held. Thereby, the logic scan chain 15 provided previously for a logic test is utilized effectively for a memory test, and information about defective places and the number of defect of one or more can be obtained in the logic scan chain 15 with a BIST test of only one time without adding complex circuit constitution.
申请公布号 JP2002032998(A) 申请公布日期 2002.01.31
申请号 JP20000214821 申请日期 2000.07.14
申请人 FUJITSU LTD 发明人 SUZUKI MASAHITO
分类号 G01R31/28;G06F12/16;G11C29/02;G11C29/12;G11C29/44;(IPC1-7):G11C29/00 主分类号 G01R31/28
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