发明名称 |
Packet switch with one-stop buffer in memory with massive parallel access |
摘要 |
A broadband packet switch that handles all packets that arrive within the same frame time by simultaneously bit-pipelining the packets into different sections of the one-stop packet buffer through an input switch. Each packet remains in is selected section until its eventual exit from the buffer through an output switch. Access to the memory storage in which the packet buffer resides is not through a memory bus or buses, thereby engendering massive parallel access.
|
申请公布号 |
US2002012356(A1) |
申请公布日期 |
2002.01.31 |
申请号 |
US20010882760 |
申请日期 |
2001.06.15 |
申请人 |
LI SHUO-YEN ROBERT;ZHU JIAN |
发明人 |
LI SHUO-YEN ROBERT;ZHU JIAN |
分类号 |
G02B6/35;G06F7/50;H04J3/24;H04L12/28;H04L12/40;H04L12/50;H04L12/54;H04L12/56;H04Q11/00;(IPC1-7):H04L12/54 |
主分类号 |
G02B6/35 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|